{"id":23,"date":"2017-06-23T04:08:12","date_gmt":"2017-06-23T04:08:12","guid":{"rendered":"http:\/\/mooney.gatech.edu\/security\/?page_id=23"},"modified":"2026-02-25T15:16:25","modified_gmt":"2026-02-25T20:16:25","slug":"publications","status":"publish","type":"page","link":"https:\/\/mooney.gatech.edu\/security\/publications\/","title":{"rendered":"Publications"},"content":{"rendered":"

Publications (as of February 2026)<\/h2>\r\n
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DISCLAIMER<\/em><\/p>\r\n

WARNING<\/strong>: This directory contains PDF\/PS files of articles that may be covered by copyright. You may browse the articles at your convenience, (in the same spirit as you may read a journal or a proceeding article in a public library). Retrieving, copying, or or distributing these files may violate copyright protection laws. We recommend that the user abide by U.S. and international law in accessing this directory.<\/p>\r\n

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Theses Supervised<\/h3>\r\n

Kevin Hutto, “Remote Sensor Security Through Encoded Computation and Cryptographic Signatures<\/a>,” Ph.D dissertation, Georgia Institute of Technology, Atlanta, Spring 2024.\u00a0 Presentation (pdf)<\/span><\/a><\/p>\r\n

Yu-Cheng Chen, “Cyber Threat Propagation Modeling In Cyber Physical Systems<\/a>,” Ph.D. dissertation, Georgia Institute of Technology, Atlanta, Spring 2022. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

Taimour Webhe, “ Medical Device Security Through Hardware Signatures<\/a>,”Ph.D. dissertation, Georgia Institute of Technology, Atlanta, Fall 2018. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

Jun Cheol Park, “Sleepy Stack: a New Approach to Low Power VLSI and Memory<\/a>,” Ph.D. dissertation, Georgia Institute of Technology, Atlanta, Summer 2005. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

Yudong Tan, “Cache Design and Timing Analysis for Preemptive Multi-tasking Real-Time Uniprocessor Systems<\/a>,” Ph.D. dissertation, Georgia Institute of Technology, Atlanta, Spring 2005. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

Jaehwan Lee, “Hardware\/Software Deadlock Avoidance for Multiprocessor Multiresource System-on-a-Chip<\/a>,” Ph.D. dissertation, Georgia Institute of Technology, Atlanta, Fall 2004. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

Kyeong Keol Ryu, “Automated Bus Generation for Multiprocessor SoC Design<\/a>,” Ph.D. dissertation, Georgia Institute of Technology, Atlanta, Summer 2004. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

Tankut Akgul, “Assembly Instruction Level Reverse Execution for Debugging<\/a>,” Ph.D. dissertation, Georgia Institute of Technology, Atlanta, Spring 2004. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

Pramote Kuacharoen, “Embedded Software Streaming via Block Streaming<\/a>,” Ph.D. dissertation, Georgia Institute of Technology, Atlanta, Spring 2004. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

Bilge E. S. Akgul, “The System-on-a-Chip Lock Cache<\/a>,” Ph.D. dissertation, Georgia Institute of Technology, Atlanta, Spring 2004. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

Eung Seo Shin, “Automated Generation of Round-robin Arbitration and Crossbar Switch Logic<\/a>,” Ph.D. dissertation, Georgia Institute of Technology, Atlanta, Fall 2003. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

Mohamed A. Shalan, “Dynamic Memory Management for Embedded Real-Time Multiprocessor System-on-a-Chip<\/a>,” Ph.D. dissertation, Georgia Institute of Technology, Atlanta, Fall 2003. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

Thesis<\/b><\/h3>\r\n

V. Mooney, “Hardware\/Software Codesign of Run-Time Systems<\/a>,” Technical Report CSL-TR-98-762<\/a>, Stanford Computer Science Department Electronic Library, June 1998.<\/p>\r\n

Books<\/b><\/h3>\r\n

R. Reis, V. Mooney and P. Hasler, editors, VLSI-SoC: Advanced Topics on Systems on a Chip<\/b><\/a>, Springer Science+Business Media: New York, 2008.<\/p>\r\n

M. Glesner, R. Reis, L. Indrusiak, V. Mooney and H. Eveking, editors, VLSI-SoC: From Systems to Chips<\/b><\/a>, Springer Science+Business Media: New York, 2006.<\/p>\r\n

Journals\/Book Chapters<\/b><\/p>\r\n

D. Gordon, A. Allahverdi, S. Abrelat, A. Hemingway, A. Farooq, I. Smith, N. Arora, A. Chang, Y. Qiang and V. Mooney, “Scalable Nonlinear Sequence Generation using Composite Mersenne Product Registers<\/a>,” IACR Communications in Cryptology, 1(4), pp. 1-77, January 2025, https:\/\/doi.org\/10.62056\/a3tx11zn4.<\/p>\r\n

K. Hutto, V. Mooney, “Implementing a Privacy Homomorphism with Random Encoding and Computation Controlled by a Remote Secure Server<\/a>,” ACM Transactions on Embedded Computing<\/em>, 25(2), pp. 1-27, January 2025, https:\/\/dl.acm.org\/doi\/10.1145\/3651617.<\/p>\r\n

Y. Chen, V. Mooney and S. Grijalva, “Grid Cyber-Security Strategy in an Attacker-Defender Model<\/a>,” MDPI Journal of Cryptography<\/em>, (Special Issue on Feature Papers on Hardware Security), 5(2), 12, April 2021.<\/p>\r\n

P. Coppock, M. Yacoub, B. Qin, A. Daftardar, Z. Tolaymat and V. Mooney, “Hardware Root-of-Trust-based Integrity for Shared Library Function Pointers in Embedded Systems<\/a>,” Microprocessors and Microsystems<\/em> (Special Issue on Embedded Computing – MECO 2019), 79, 103270, November 2020.<\/p>\r\n

T. Wehbe, V. Mooney and D. Keezer, “Hardware-Based Run-Time Code Integrity in Embedded Devices<\/a>,”\u00a0MDPI Journal of Cryptography (Special Issue on Physical Layer Security and Trust for Legacy Systems and Supply Chain Assurance)<\/span>, 2(3), 20, August 2018.<\/p>\r\n

T. Wehbe, V. Mooney, O. Inan and D. Keezer, “Securing Medical Devices Against Hardware Trojan Attacks Through Analog-, Digital-, and Physiological-Based Signatures<\/a>,” Journal of Hardware and Systems Security (Special Issue on Hardware Solutions for Cyber Security)<\/span>, June 2018.<\/p>\r\n

C. Dhoot, L.P. Chau, S.R. Chowdhury and V. Mooney, “Low Power Motion Estimation Based on Probabilistic Computing<\/a>,”IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), 24(1), pp. 1-14, January 2014.<\/p>\r\n

A. Singh, A. Basu, K.V. Ling and V. Mooney, “Models for Characterizing Noise Based PCMOS Circuits<\/a>,” ACM Transactions on Embedded Computing Systems<\/a>, 13(1s), November 2013.<\/p>\r\n

J.C. Park and V. Mooney, “Pareto Points in SRAM Design Using the Sleepy Stack Approach,” in the book VLSI-SoC: From Systems to Silicon<\/b><\/a>, edited by Ricardo Reis, Adam Osseiran and Hans-Joerg Pfleiderer, published by Springer Science+Business Media: New York, pp. 163-177, 2007.<\/p>\r\n

J. Lee and V. Mooney, “A Novel O(n) Parallel Banker’s Algorithm for System-on-a-Chip,” IEEE Transactions on Parallel and Distributed Systems<\/a>, 17(12), 1377-1389, December 2006.<\/p>\r\n

J.C. Park and V. Mooney, “Sleepy Stack Leakage Reduction,” <\/a>IEEE Transactions on VLSI<\/a>, 14(11), 1250-1263, November 2006.<\/p>\r\n

J. Lee and V. Mooney, “Hardware\/Software Partitioning of Operating Systems: Focus on Deadlock Avoidance,” Chapter 4 in the book System On Chip: Next Generation Electronics<\/a>, edited by Bashir M. Al-Hashimi, IEE, United Kingdom, 2006.<\/p>\r\n

J. Lee and V. Mooney, “ An O(min(m,n)) Parallel Deadlock Detection Algorithm,” <\/a>ACM Transactions on Design Automation of Electronic Systems<\/a>, 10(3), 573-586, July 2005.<\/p>\r\n

J. Lee and V. Mooney, “Hardware\/Software Partitioning of Operating Systems: Focus on Deadlock Detection and Avoidance,”<\/a> IEE Proceedings on Computers and Digital Techniques<\/a>, 152(2), pp. 167-182, March 2005.<\/p>\r\n

P. Kuacharoen, V. Mooney and V. Madisetti, “Stream-Enabled File I\/O for Embedded Systems<\/a>,” KMITL Science Journal, Special Issue International Symposium on Mathematical, Statistical and Computer Sciences<\/a>, 5(1), pp. 62-75, February 2005.<\/p>\r\n

K. Ryu and V. Mooney, “Automated Bus Generation for Multiprocessor SoC Design<\/a>,”
IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems (TCAD)<\/a>, 23(11), pp. 1531-1549, November 2004.<\/p>\r\n

T. Akgul and V. Mooney, “Assembly Instruction Level Reverse Execution for Debugging<\/a>,” ACM Transactions on Software Engineering and Methodology (TOSEM)<\/a>, 13(2), pp. 149-198, April 2004.<\/p>\r\n

J.C. Park, V. Mooney and S. Srinivasan, “Combining Data Remapping and Voltage\/Frequency Scaling of Second Level Memory for Energy Reduction in Embedded Systems<\/a>,” Microelectronics Journal<\/a>, 34(11), pp. 1019-1024, November 2003.<\/p>\r\n

V. Mooney, “Hardware\/Software Partitioning of Operating Systems,” in the book Embedded Software for SoC<\/b><\/a>, edited by Ahmed Amine Jerraya, Sungjoo Yoo, Diederik Verkest and Norbert Wehn, published by Kluwer Academic Publishers, Boston, MA, U.S.A, pp. 187-206, September 2003.<\/p>\r\n

P. Kuacharoen, V. Mooney and V. Madisetti, “Software Streaming via Block Streaming,” in the book Embedded Software for SoC<\/b><\/a>, edited by Ahmed Amine Jerraya, Sungjoo Yoo, Diederik Verkest and Norbert Wehn, published by Kluwer Academic Publishers, Boston, MA, U.S.A, pp. 435-448, September 2003.<\/p>\r\n

V. Mooney and D. Blough, “A Hardware-Software Real-Time Operating System Framework for SOCs<\/a>,” IEEE Design and Test of Computers,<\/a> pp. 44-51, November-December 2002.<\/p>\r\n

B. E. S. Akgul and V. Mooney, “The System-on-a-Chip Lock Cache<\/a>,” International Journal of Design Automation for Embedded Systems, 7(1-2), pp. 139-174, September 2002.<\/p>\r\n

K. Puttaswamy, L. Chakrapani, K. Choi, Y. Dhillon, U. Diril, P. Korkmaz, K. Lee, J.C. Park, A. Chatterjee, P. Ellervee, V. Mooney, K. Palem and W. Wong, “Power-Performance Trade-Offs in Second Level Memory Used by an ARM-Like RISC Architecture,” in the book Power Aware Computing<\/b><\/a>, edited by Rami Melhem, University of Pittsburgh, PA, USA and Robert Graybill, DARPA\/ITO, Arlington, VA, USA, published by Kluwer Academic\/Plenum Publishers, pp. 211-224, May 2002.<\/p>\r\n

V. Mooney and G. De Micheli, “Hardware\/Software Codesign of Run-Time Schedulers for Real-Time Systems<\/a>,”Design Automation of Embedded Systems<\/em>, 6(1), pp. 89-144, September 2000.<\/p>\r\n

W. Shields Neely and V. Mooney, “System Level Design for System on a Chip<\/a>,” Design Automation of Embedded Systems<\/em>, 3(4), pp. 291-309, September 1998.<\/p>\r\n

Conference\/Workshop Proceedings<\/b><\/h3>\r\n

A. Allahverdi, K. Ahmad, S. Grijalva and V. Mooney, “A Lightweight Cryptographic Permutation Generator for Critical Infrastructure Protection,<\/a>” 2026 Texas Power and Energy Conference<\/span>, February 2026. Presentation (pdf)<\/span><\/a><\/p>\r\n

K. Ahmad, A. Allahverdi, S. Grijalva and V. Mooney, “GridLogic 2FA: Two-Factor Authentication for Critical Infrastructure Commands in the Field<\/a>,” 2026 Texas Power and Energy Conference<\/span>, February 2026. Presentation (pdf)<\/span><\/a><\/p>\r\n

S. Grijalva, V Mooney, T. Lewis et al<\/em>., “Experimental Evaluation of a Novel Hardware-Based Authentication Solution for Securing Electrical Grids,” in\u00a0IEEE Transactions on Industry Applications<\/em>, doi: 10.1109\/TIA.2025.3606453.<\/p>\r\n

C. K\u00f6rpe,\u00a0K. Ahmad,\u00a0E. \u00d6zt\u00fcrk,\u00a0K. Tihaiya,\u00a0R. Tran,\u00a0H. Yang,\u00a0J. Yang, G. D\u00fcndar, V. Mooney and K. Ozanoglu, \u201cA Side-Channel Attack-Resilient Single-Slope ADC for Image Sensor Applications,\u201d<\/a>\u00a021st<\/sup>\u00a0International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design<\/i> (SMACD’25), July 2025. Presentation (pdf)<\/span><\/a><\/p>\r\n

A. Allahverdi\u00a0and V. Mooney, \u201cA Hardware-Efficient AEAD Stream Cipher Based on a Hybrid Nonlinear Feedback Register Structure,\u201d<\/a>\u00a02025 IEEE International Conference on Cyber Security and Resilience<\/i> (CSR’25), August 2025. Presentation (pdf)<\/span><\/a> Corrected Paper (fixes a small typo in Table I)<\/span><\/a><\/p>\r\n

K. Ahmad,\u00a0E. \u00d6zt\u00fcrk,\u00a0C. K\u00f6rpe,\u00a0H. Yang,\u00a0J. Yang,\u00a0K. Tihaiya,\u00a0R. Tran, G. D\u00fcndar, V. Mooney and K. Ozanoglu, \u201cProtection of the Digital Circuitry of a Single-Slope ADC Against Side-Channel Attacks,\u201d<\/a>\u00a02025 IEEE International Conference on Cyber Security and Resilience<\/i> (CSR’25), August 2025. Presentation (pdf)<\/span><\/a><\/p>\r\n

Best Paper Award<\/strong>: O. Blanchette, G. Calderon, A. Hamby, J. Liu, V. Rubanova and V. Mooney, “Linguistic Encryption for Underwater Communication<\/a>,” 2024 13th Mediterranean Conference on Embedded Computing (MECO’24), June 2024. Presentation (pdf)<\/a><\/span><\/p>\r\n

J. Keller, K. Hutto, S. Grijalva, V. Mooney, T. Lewis, R. Barrett, B. Holland and E. Patten, “Experimental System for Supply Chain Cyber-Security of Distribution Switch Controls<\/a>,” 2024 Texas Power and Energy Conference<\/span>, February 2024.<\/p>\r\n

J. Keller, S. Paul, K. Hutto, S. Grijalva and V. Mooney, “Developing Simulation Capabilities for Supply Chain Cybersecurity of the Electricity Grid<\/a>,” 2023 IEEE PES Innovative Smart Grid Technologies Latin America (ISGT-LA’23), pp. 205-209, November 2023.<\/p>\r\n

K. Hutto and V. Mooney, “Late Breaking Results: COPPER: Computation Obfuscation by Producing Permutations for Encoding Randomly,<\/a>” 2023 60th Design Automation Conference (DAC 60), July 2023.<\/p>\r\n

Y. Tan, A. Diwakar, J. Jagielo and V. Mooney, “Software Compilation Using FPGA Hardware: Register Allocation<\/a>,” 2023 12th Mediterranean Conference on Embedded Computing (MECO’23), June 2023. Presentation (pdf)<\/a><\/span><\/p>\r\n

J. Keller, S. Paul, S. Grijalva and V. Mooney, \u201cExperimental Setup for Grid Control Device Software Updates in Supply Chain Cyber-Security<\/a>,\u201d 2022 54th<\/sup> North American Power Symposium (NAPS\u201922), October 2022. Presentation (pdf)<\/a><\/span><\/p>\r\n

Best Paper Award<\/strong>: K. Hutto, S. Grijalva and V. Mooney, “RanCompute: Computational Security in Embedded Devices via Random Input and Output Encodings<\/a>,” 2022 11th Mediterranean Conference on Embedded Computing (MECO’22), June 2022. Presentation (pdf)<\/span><\/a><\/p>\r\n

K. Hutto, S. Paul, B. Newberg, V. Boyapati, Y. Vunnam, S. Grijalva and V. Mooney, “PUF-Based Two-Factor Authentication Protocol for Securing the Power Grid Against Insider Threat<\/a>,” Kansas Power and Energy Conference (KPEC’22), April 2022. Presentation (pdf)<\/a><\/span><\/p>\r\n

B. Newberg, S. Grijalva and V. Mooney, “Open-Source Architecture for Multi-Party Update<\/a> Verification for Data Acquisition Devices,” Power and Energy Conference at Illinois<\/span>, March 2022. Presentation (pdf)<\/a><\/span><\/p>\r\n

K. Hutto, S. Grijalva and V. Mooney, “Hardware-Based Randomized Encoding for Sensor Authentication in Power Grid SCADA Systems<\/a>,<\/span>” 2022 Texas Power and Energy Conference<\/span>, February 2022. Presentation (pdf)<\/span><\/a><\/p>\r\n

S. Paul, Y. Chen, S. Grijalva and V. Mooney, “A Cryptographic Method for Defense Against MiTM Cyber Attack in the Electricity Grid Supply Chain<\/a>,” 2022 IEEE PES Innovative Smart Grid Technologies Conference (ISGT’22), pp. 1-5, February 2022.<\/p>\r\n

B. Semiz, M. Emre Gursoy, M. Hasan Shandhi, L. Orlandic, V. Mooney and O. Inan, “Automatic Subject Identification Using Scale-Based Ballistocardiogram Signals<\/a>,” EAI Mobihealth 2021, November 2021.<\/p>\r\n

K. Hutto and V. Mooney, “Sensing with Random Encoding for Enhanced Security in Embedded Systems<\/a>,” 2021 10th Mediterranean Conference on Embedded Computing (MECO’21)<\/a>, pp. 809-814, June 2021. Presentation (pdf)<\/span><\/a><\/p>\r\n

Y. Chen, V. Mooney and S. Grijalva, “Electricity Grid Cyber-Physical Security Risk Assessment Using Simulation of Attack Stages and Physical Impact<\/a>,” Kansas Power and Energy Conference (KPEC’20), July 2020.<\/p>\r\n

Y. Chen, V. Mooney and S. Grijalva, “Grid Cyber-Security Strategy Assessment in an Attacker-Defender Model,” IEEE Power Systems Conference (PSC’20)<\/a>, March 2020.<\/p>\r\n

Y. Chen, V. Mooney and S. Grijalva, “A Survey of Attack Models for Cyber-Physical Security Assessment in Electricity Grid,” Proceedings of the IFIP Working Group 10.5 Very Large Scale Integration System-on-a-Chip (VLSI-SoC 2019), October 2019.<\/p>\r\n

G. Lopez, M. Foreman, A. Daftardar, P. Coppock, Z. Tolaymat and V. Mooney, \u201c Hardware Root-of-Trust Based Integrity for Shared Library Function Pointers in Embedded Systems<\/a>,\u201d 2019 8th Mediterranean Conference on Embedded Computing (MECO’19)<\/a>, pp. 196-201, June 2019.<\/p>\r\n

Y. Chen, D. Campbell, V. Mooney, S. Grijalva, B. Eames, A. Outkin, E. Vugrin, R. Helinski and B. Anthony, “Power Grid Bad Data Injection Attack Modeling in PRESTIGE,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech’19), Albuquerque, NM, March 2019.<\/p>\r\n

Y. Chen, T. Gieseking, D. Campbell, V. Mooney and S. Grijalva, “A Hybrid Attack Model for Cyber-Physical Security Assessment in Electricity Grid<\/a>,”in Texas Power and Energy Conference (TPEC), Feb. 2019.<\/p>\r\n

T. Wehbe, V. Mooney and D. Keezer, “Work-in-Progress: A Chip-Level Security Framework for Assessing Sensor Data Integrity<\/a>,” in International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS), Oct. 2018.<\/p>\r\n

V. Chukwuka, Y. Cheng, S. Grijalva and V. Mooney, “ Bad Data Injection Attack Propagation in Cyber-Physical Power Delivery Systems<\/a>,”in Power System Conference (PSC), Sep. 2018.<\/p>\r\n

T. Wehbe, V. Mooney, D. Keezer, O. Inan and A. Javaid, “Use of Analog Signatures for Hardware Trojan Detection<\/a>,”\u00a0Proceedings of the 14th FPGAworld Conference <\/em>(FPGAworld’17),\u00a0<\/em>ACM, Sept. 2017, pp. 15-22.<\/p>\r\n

T. Wehbe, V. Mooney, A. Javaid and O. Inan “A Novel Physiological Features-Assisted Architecture for Rapidly Distinguishing Health Problems from Hardware Trojan Attacks and Errors in Medical Devices<\/a>,” IEEE International Symposium on Hardware Oriented Security and Trust<\/i> (HOST’17), May 2017, pp. 106-109.
<\/p>\r\n

T. Wehbe, V. Mooney, D. Keezer and N. Parham “A Novel Approach to Detect Hardware Trojan Attacks on Primary Data Inputs<\/a>,” Proceedings of the 2015 ACM Workshop on Embedded Systems Security<\/i> (WESS’15), Article 2, 10 pages, October 2015. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

A. Gbade-Alabi, D. Keezer, V. Mooney, A. Poshmann, M. St\u00f6ttinger and K. Divekar, “A Signature Based Architecture for Trojan Detection<\/a>,” Proceedings of the 2014 ACM Workshop on Embedded Systems Security<\/i> (WESS’14), October 2014.\u00a0Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

<\/p>\r\n

A. Heinig, V. Mooney, F. Schmoll, P. Marwedel, K. Palem and M. Engel, “Classification-based Improvement of Application Robustness and Quality of Service in Probabilistic Computer Systems<\/a>,” Architecture of Computing Systems<\/i> (ARCS 2012), March 2012, Winner of the ARCS 2012 Best Paper Award.<\/p>\r\n

C. Dhoot, V. Mooney, S.R. Chowdhury and L.P. Chau, “Fault Tolerant Design for Low Power Hierarchical Search Motion Estimation Algorithms<\/a>,” Proceedings of the IFIP Working Group 10.5 Very Large Scale Integration System-on-a-Chip<\/i> (VLSI-SoC’11), October 2011. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

Z. Kedem, V. Mooney, K.K. Muntimadugu and K. Palem, “An Approach to Energy-Error Tradeoffs in Approximate Ripple Carry Adders<\/a>,” Proceedings of the International Symposium on Low Power Electronics and Design<\/i> (ISLPED 2011), pp. 211-216, August 2011. Poster (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

A. Singh, S. Mandavalli, V. Mooney and K.V. Ling, “A Novel and Fast Method for Characterizing Noise Based PCMOS Circuits<\/a>,”
Proceedings of the Asian Symposium on Quality Electronic Design<\/i> (ASQED 2011), July 2011. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

A. Gupta, S. Mandavalli, V. Mooney, K.V. Ling, A. Basu, H. Johan and B. Tandianus, “Low Power Probabilistic Floating Point Multiplier Design<\/a>,” Proceedings of the IEEE Computer Society Annual Symposium on VLSI<\/i> (ISVLSI 2011), pp. 182-187, July 2011. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

C. Dhoot, V. Mooney, L.P. Chau and S.R. Chowdhury, “Low Power Motion Estimation with Probabilistic Motion Estimation<\/a>,” Proceedings of the IEEE Computer Society Annual Symposium on VLSI<\/i> (ISVLSI 2011), pp. 176-181, July 2011.<\/p>\r\n

A. Singh, A. Basu, K.V. Ling and V. Mooney, “Modeling Multi-output Filtering Effects in PCMOS<\/a>,” Proceedings of the VLSI Design and Test Conference<\/i> (VLSIDAT 2011), April 2011. Poster (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

Z. Kedem, V. Mooney, K.K. Muntimadugu, K. Palem, A. Devarasetty and P.D. Parasuramuni, “Optimizing Energy to Minimize Errors in Dataflow Graphs Using Approximate Adders<\/a>,” Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems<\/i> (CASES 2010), pp. 177-186, October 2010.<\/p>\r\n

M. Lau, K.V. Ling, A. Bhanu and V. Mooney, “Error Rate Prediction for Probabilistic Circuits with More General Structures<\/a>,” Proceedings of the 16th Workshop on Synthesis And System Integration of Mixed Information technologies<\/i> (SASIMI’10), pp. 220-225, April 2010. Poster (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

A. Bhanu, M. Lau, K. Ling, V. Mooney and A. Singh, “A More Precise Model of Noise Based CMOS Errors<\/a>,” Proceedings of the 5th International Symposium on Electronic Design, Test and Applications<\/i> (DELTA’10), pp. 99-102, January 2010. Poster (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

K. Palem, A. Barr, A. Lingamneni, V. Mooney, R. Pingali, H. Sampath and J. Sivaswamy, I-Slate, “Ethnomathematics and Rural Education<\/a>,” Proceedings of the IEEE Conference on Technologies for Humanitarian Challenges<\/i>, August 2009.<\/p>\r\n

F. Zhang, K. Szwaykowska, W. Wolf and V. Mooney, “Task Scheduling for Control Oriented Requirements for Cyber-Physical Systems<\/a>,” Proceedings of the IEEE Real-Time Systems Symposium<\/i> (RTSS’08), pp. 47-56, December 2008.<\/p>\r\n

L. Zhao, D. Blough, V. Mooney and J. Fiore, “ An Approach Using the Data Distribution Service as the Connecting Transport for 100X Joint Battlespace Infosphere Servers<\/a>,” High Performance Embedded Computing<\/i> (HPEC’08), September 2008.<\/p>\r\n

<\/p>\r\n

S. Kim and V. Mooney, “Sleepy Keeper: A New Approach to Low-Leakage Power VLSI Design<\/a>,” Proceedings of the IFIP Working Group 10.5 Very Large Scale Integration System-on-a-Chip<\/i> (VLSI-SoC’06), pp. 367-372, October 2006. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

J.C. Park and V. Mooney, “Pareto Points in SRAM Design Using the Sleepy Stack Approach<\/a>,” Proceedings of the IFIP Working Group 10.5 Very Large Scale Integration System-on-a-Chip<\/i> (VLSI-SoC’05), pp.239-244, October 2005. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

Y. Tan and V. Mooney, “WCRT Analysis for a Uniprocessor with a Unified Prioritized Cache<\/a>,” Proceedings of the 2005 ACM SIGPLAN\/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems<\/i> (LCTES’05), pp.175-182, June 2005. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

J. Lee and V. Mooney, “A novel O(n) Parallel Banker’s Algorithm for System-on-a-Chip<\/a>,” Proceedings of the Asia and South Pacific Design Automation Conference<\/i> (ASPDAC’05), pp.1304-1308, January 2005. Poster (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

J.C. Park, V. Mooney and P. Pfeiffenberger, “Sleepy Stack Reduction in Leakage Power<\/a>,” Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation<\/i> (PATMOS’04), pp.148-158, September 2004. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

J. Lee and V. Mooney, “A Novel Deadlock Avoidance Algorithm and Its Hardware Implementation<\/a>,” Proceedings of the International Conference on Hardware\/Software Codesign and System Synthesis<\/i> (CODES-ISSS’04), pp.200-205, September 2004. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

Y. Tan and V. Mooney, “Integrated Intra- and Inter-Task Cache Analysis for Preemptive Multi-tasking Real-Time Systems<\/a>,” Proceedings of 8th International Workshop on Software and Compilers for Embedded Systems<\/i> (SCOPES’04), pp.182-199, September 2004. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

P. Kuacharoen, V. Mooney and V. Madisetti, “Efficient Execution of Large Applications on Portable and Wireless Clients<\/a>,” Proceedings of the Mobility Conferences<\/i>, August 2004.
<\/p>\r\n

K. Ryu, A. Talpasanu, V. Mooney and J. Davis, “Interconnect Delay Aware RTL Verilog Bus Architecture Generation for an SoC<\/a>,” Proceedings of the IEEE Asia-Pacific Conference on Advanced System Integrated Circuits <\/i>(AP-ASIC’04), pp.176-179, August 2004. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

O. Celebican, T. Simunic Rosing and V. Mooney, “Energy Estimation of Peripheral Devices in Embedded Systems<\/a>,” Proceedings of the 2004 ACM Great Lakes Symposium on VLSI<\/i> (GLVLSI’04), pp.430-435, April 2004. Poster (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

Y. Tan and V. Mooney, “Timing Analysis for Preemptive Multi-Tasking Real-Time Systems with Caches<\/a>,” Proceedings of the Design, Automation and Test in Europe Conference<\/i> (DATE’04), pp.1034-1039, February 2004. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

A. Balasundaram, A. Pereira, J.C. Park and V. Mooney, “Golay and Wavelet Error Control Codes in VLSI<\/a>,” Proceedings of the Asia and South Pacific Design Automation Conference<\/i> (ASPDAC’04), pp.563-564, January 2004. Presentation (pdf)<\/span><\/span><\/span><\/a> Poster (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

B. E. S. Akgul, V. Mooney, H. Thane and P. Kuacharoen, “Hardware Support for Priority Inheritance<\/a>,” Proceedings of the IEEE Real-Time Systems Symposium<\/i> (RTSS’03), pp.246-254, December 2003. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

P. Kuacharoen, M. Shalan and V. Mooney, “A Configurable Hardware Scheduler for Real-Time Systems<\/a>,” Proceedings of the International Conference on
Engineering of Reconfigurable Systems and Algorithms<\/i> (ERSA’03), pp.96-101, June 2003. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

Y. Tan and V. Mooney, “A Prioritized Cache for Multi-tasking Real-Time Systems<\/a>,” Proceedings of the 11th Workshop on Synthesis And System Integration of Mixed Information technologies<\/i> (SASIMI’03), pp. 168-175, April 2003. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

M. Shalan, E. Shin and V. Mooney, “DX-Gt: Memory Management and Crossbar Switch Generator for Multiprocessor System-on-a-Chip<\/a>,” Proceedings of the 11th Workshop on Synthesis And System Integration of Mixed Information technologies<\/i> (SASIMI’03), pp. 357-364, April 2003. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

K. Ryu and V. Mooney, “Automated Bus Generation for Multiprocessor SoC
Design<\/a>,” Proceedings of the Design Automation and Test in Europe Conference<\/i> (DATE’03), pp. 282-287, March 2003. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

V. Mooney, “Hardware\/Software Partitioning of Operating Systems<\/a>,” Proceedings of the Design Automation and Test in Europe Conference<\/i> (DATE’03), pp. 338-339, March 2003. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

P. Kuacharoen, V. Mooney and V. Madisetti, “Software Streaming via Block Streaming<\/a>,” Proceedings of the Design Automation and Test in Europe Conference<\/i> (DATE’03), pp. 912-917, March 2003. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

B. E. S. Akgul and V. Mooney, “PARLAK: Parametrized Lock Cache Generator<\/a>,” Proceedings of the Design Automation and Test in Europe Conference<\/i> (DATE’03), pp. 1138-1139, March 2003. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

J. Lee, V. Mooney, A. Daleby, K. Ingstrom, T. Klevin and L. Lindh, “A Comparison of the RTU Hardware RTOS with a Hardware\/Software RTOS<\/a>,” Proceedings of the Asia and South Pacific Design Automation Conference<\/i> (ASPDAC’03), pp. 683-688, January 2003. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

J.C. Park, V. Mooney, K. Palem and K. Choi, “Energy Minimization of a Pipelined Processor using a low Voltage Pipelined Cache<\/a>,” Proceedings of 36th Annual Asilomar Conference on Signals, Systems and Computers<\/i> (ASILOMAR’02), pp. 67-73, November 2002. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

T. Akgul and V. J. Mooney, “Instruction-level Reverse Execution for Debugging<\/a>,” Proceedings of the Workshop on Program Analysis for Software Tools and Engineering<\/i> (PASTE’02), pp. 18-25, November 2002. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

E. Shin, V. Mooney and G. Riley, “Round-robin Arbiter Design and Generation<\/a>,” Proceedings of the International Symposium on System Synthesis<\/i> (ISSS’02), pp. 243-248, October 2002. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

K. Puttaswamy, K. Choi, J.C. Park, V. Mooney, A. Chatterjee and P. Ellervee, “System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory<\/a>,” Proceedings of the International Symposium on System Synthesis<\/i> (ISSS’02), pp. 225-230, October 2002. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

S. Srinivasan, J.C. Park and V. Mooney, “Combining Data Remapping and Voltage\/Frequency Scaling of Second Level Memory for Energy Reduction in Embedded Systems<\/a>,” Proceedings of the First International Workshop on Embedded System Codesign<\/i> (ESCODES’02), pp. 57-62, September 2002. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

J. Lee, K. Ryu and V. Mooney, “A Framework for Automatic Generation of Configuration Files for a Custom Hardware\/Software RTOS<\/a>,” Proceedings of the International Conference
on Engineering of Reconfigurable Systems
and Algorithms<\/i> (ERSA’02), pp. 31-37, June 2002. Presentation (pdf)<\/span><\/span><\/span> <\/a><\/p>\r\n

K. Palem, R. Rabbah, V. Mooney, P. Korkmaz and K. Puttaswamy, “Design Space Optimization of Embedded Memory Systems via Data Remapping<\/a>,” Proceedings of the Joint Conference on Languages, Compilers, and Tools for Embedded Systems and Software and Compilers for Embedded Systems<\/i> (LCTES’02-SCOPES-02), pp. 28-37, June 2002. Presentation (pdf)<\/span><\/span><\/span> <\/a><\/p>\r\n

M. Shalan and V. Mooney, “Hardware Support for Real-Time Embedded Multiprocessor System-on-a-Chip Memory Management<\/a>,” Proceedings of the Tenth International Symposium on Hardware\/Software Codesign<\/i> (CODES’02), pp. 79-84, May 2002. Presentation (pdf)<\/span><\/span><\/span> <\/a><\/p>\r\n

L.Chakrapani, P. Korkmaz, V. Mooney, K. Palem, K. Puttaswamy and W. Wong, “The Emerging Power Crisis in Embedded Processors: What can a (poor) Compiler do?<\/a>,” Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems <\/i> (CASES’01), pp. 176-180, November 2001. Presentation (pdf)<\/span><\/span><\/span><\/a><\/p>\r\n

B. E. S. Akgul, J. Lee and V. Mooney, “A System-on-a-Chip Lock Cache with Task Preemption Support<\/a>,” Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems <\/i> (CASES’01), pp. 149-157, November 2001. Presentation (pdf)<\/a><\/span><\/span><\/p>\r\n

T. Akgul, P. Kuacharoen, V. Mooney and V. Madisetti, “A Debugger RTOS for Embedded Systems<\/a>,” Proceedings of the 27th EUROMICRO Conference<\/i> (EUROMICRO’01), pp. 264-269, September 2001. Presentation (pdf)<\/a><\/span><\/span><\/p>\r\n

P. Kuacharoen, T. Akgul, V. Mooney and V. Madisetti, “Adaptability, Extensibility, and Flexibility in Real-Time Operating Systems<\/a>,” Proceedings of the EUROMICRO Symposium on Digital Systems Design <\/i> (EUROMICRO’01), pp. 400-405, September 2001. Presentation (pdf)<\/a><\/span><\/span><\/p>\r\n

K. Ryu, E. Shin and V. Mooney, “A Comparison of Five Different Multiprocessor SoC Bus Architectures<\/a>,” Proceedings of the EUROMICRO Symposium on Digital Systems Design<\/i> (EUROMICRO’01), pp. 202-209, September 2001. Presentation (pdf)<\/a><\/span><\/span><\/p>\r\n

P. Shiu, Y. Tan and V. Mooney, “A Novel Parallel Deadlock Detection Algorithm and Architecture<\/a>,” 9th International Workshop on Hardware\/Software Codesign<\/i> (CODES’01), pp. 30-36, April 2001. Presentation (pdf)<\/a><\/span><\/span><\/span><\/p>\r\n

B. E. Saglam (Akgul) and V. Mooney, <\/span>“System-on-a-Chip Processor Synchronization Support in Hardware<\/a>,” Proceedings of the Design, Automation and Test in Europe Conference<\/i> (DATE’01), pp. 633-639, March 2001.<\/span><\/span> Presentation (pdf)<\/a><\/span><\/span><\/span><\/p>\r\n

M. Shalan and V. Mooney, “A Dynamic Memory Management Unit for Embedded Real-Time System-on-a-Chip<\/a><\/span>,” International Conference on Compilers, Architecture and Synthesis for Embedded Systems<\/i> (CASES’00), pp. 180-186, November 2000. Presentation (pdf)<\/a><\/span><\/span><\/span><\/p>\r\n

V. Mooney, “Path-Based Edge Activation for Dynamic Run-Time Scheduling<\/a>,”International Symposium on System Synthesis<\/i> (ISSS’99), pp. 30-36, November 1999. Presentation (pdf)<\/a> <\/span><\/span><\/span><\/p>\r\n

V. Mooney, D. Ruspini, O. Khatib and G. De Micheli, “Hardware-Software Run-Time Systems and Robotics: A Case Study<\/a>,” Euromicro Conference<\/i>, pp. 162-167, Vasteras, Sweden, August 1998.<\/p>\r\n

V. Mooney and G. De Micheli, “Real Time Analysis and Priority Scheduler Generation for Hardware-Software Systems with a Synthesized Run-Time System<\/a>,” International Conference on Computer-Aided Design<\/i> (ICCAD’97), pp. 605-612, November 1997.<\/p>\r\n

V. Mooney, T. Sakamoto and G. De Micheli, “Run-Time Scheduler Synthesis For Hardware-Software Systems and Application to Robot Control Design<\/a>,” 5th International Workshop on Hardware\/Software Codesign<\/i> (CODES’97), pp. 95-99, March 1997.<\/p>\r\n

V. Mooney, C. Coelho, T. Sakamoto and G. De Micheli, “Synthesis From Mixed Descriptions<\/a>,” European Design Automation Conference<\/i>, pp. 114-119, September 1996.<\/p>\r\n

V. Mooney, C.Coelho and G. De Micheli, “A Multiple Paradigm Front-End for Hardware-Software Synthesis,” HILES Workshop<\/i>, November 1995.<\/p>\r\n

C. Coelho, J. Yang, V. Mooney and G. De Micheli, “Redesigning Hardware-Software Systems<\/a>,” Third International Workshop on Hardware\/Software Codesign<\/i> (CODES’94), pp. 116-123, September 1994.<\/p>\r\n

Keynote Presentations<\/b><\/h3>\r\n

V. Mooney, “Research Trends in Hardware\/Software Codesign of Embedded Operating Systems for FPGAs<\/a>,” FPGAworld Conference<\/i><\/a>, Stockholm, Sweden, September 2007.<\/p>\r\n

V. Mooney, “Design of a Hardware\/Software RTOS for FPGAs with Processors<\/a>,” FPGAworld Conference<\/i><\/a>, Vasteras, Sweden, September 2004.<\/p>\r\n

Technical Reports <\/b><\/h3>\r\n

Z. Kedem, V. Mooney, K. Muntimadugu and K. Palem, “Optimizing Energy to Minimize Errors in Approximate Ripple Carry Adders,” Technical Report TR11-02<\/a>, Rice University, 2011.<\/p>\r\n

V. Mooney, K. Palem and R. Wunderlich, “Loss-Tolerant and Secure Embedded Computing via Inscrutable Instruction-Set Architectures (I2SA),” Technical Report GIT-CC-04-12<\/a>, Georgia Institute of Technology, 2004.<\/p>\r\n

Y. Tan and V.Mooney, “Cache-Related Timing Analysis for Multi-tasking Real-Time Systems with Nested Preemptions,” Technical Report GIT-CC-04-11<\/a>, Georgia Institute of Technology, 2004.<\/p>\r\n

P. Pfeiffenberger, J.C. Park and V. Mooney, “Some Layouts Using the Sleepy Stack Approach,” Technical Report GIT-CC-04-05<\/a>, Georgia Institute of Technology, June 2004.<\/p>\r\n

Y. Tan and V. Mooney, “Timing Analysis for Preemptive Multi-tasking Real-Time Systems with Caches,” Technical Report GIT-CC-04-02<\/a>, Georgia Institute of Technology, February 2004.<\/p>\r\n

A. Balasundaram, A. Pereira, J.C. Park and V. Mooney, “Golay and Wavelet Error Control Codes in VLSI,” Technical Report GIT-CC-03-33<\/a>, Georgia Institute of Technology, December 2003.<\/p>\r\n

J. Lee and V. Mooney, “An O(min(m,n)) Parallel Deadlock Detection Algorithm,” Technical Report GIT-CC-03-41<\/a>, Georgia Institute of Technology, September 2003.<\/p>\r\n

K Ryu and V. Mooney, “Automated Bus Generation for Multiprocessor SoC Design,” Technical Report GIT-CC-02-64<\/a>, Georgia Institute of Technology, December 2002.<\/p>\r\n

T. Akgul and V. J. Mooney, “Instruction-level Reverse Execution for Debugging<\/a>,” Technical Report GIT-CC-02-49<\/a>, Georgia Institute of Technology, September 2002.<\/p>\r\n

E. Shin, V. Mooney and G. Riley, “Round-robin Arbiter Design and Generation<\/a>,” Technical Report GIT-CC-02-38<\/a>, Georgia Institute of Technology, July 2002.<\/p>\r\n

R. Banakar, M. Ekpanyopang, K. Puttaswamy, R. Rabbah, M. Balakrishnan, V. Mooney and K. Palem, “An Access based Energy Model for the Datapath and Memory Hierarchy of HPL-PD Microarchitecture in Trimaran Framework (TRIREME)<\/a>,” Technical Report GIT-CC-02-35<\/a>, Georgia Institute of Technology, June 2002.<\/p>\r\n

D. Sun, D. Blough and V. Mooney, “Atalanta: A New Multiprocessor RTOS Kernel for System-on-a-Chip Applications<\/a>,” Technical Report GIT-CC-02-19<\/a>, Georgia Institute of Technology, April 2002.<\/p>\r\n

K. Palem, R. Rabbah, V. Mooney, P. Korkmaz and K. Puttaswamy, “Power Optimization of Embedded Memory Systems via Data Remapping<\/a>,” Technical Report GIT-CC-02-11<\/a>, Georgia Institute of Technology, February 2002.<\/p>\r\n

<\/p>\r\n

<\/p>\r\n

V. Mooney and G. De Micheli, “Hardware\/Software Codesign of Run-Time Schedulers for Real-Time Systems<\/a>,” Technical Report CSL-TR-97-739, Stanford Computer Science Department Electronic Library, November 1997. (This is an early version of the journal paper by the same title in Design Automation of Embedded Systems<\/em>, 1999).<\/p>\r\n

V. Mooney, “Searle’s Chinese Room and its Aftermath<\/a>,” Center for the Study of Language and Information, CSLI-97-202<\/a>,” June 1997.<\/p>\r\n

Unpublished Papers<\/b><\/h3>\r\n

“Verilog Simulation of a Hardware-Software Implementation of a Robotics Control Algorithms<\/a>,” F. Abdullah and V. Mooney, January 28, 1998.<\/p>\r\n

\r\n

Any suggestions, questions or concerns can be addressed to
Vincent Mooney<\/a>.<\/p>\r\n","protected":false},"excerpt":{"rendered":"

Publications (as of February 2026) DISCLAIMER WARNING: This directory contains PDF\/PS files of articles that may be covered by copyright. You may browse the articles at your convenience, (in the same spirit as you may read a journal or a proceeding article in a public library). Retrieving, copying, or or distributing these files may violate … <\/p>\n

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