Vincent John Mooney III

Georgia Institute of Technology
Associate Professor, School of Electrical and Computer Engineering
Adjunct Associate Professor, School of Computer Science, College of Computing
777 Atlantic Drive
Atlanta, GA 30332-0250
Phone: (404) 385-0437 / Fax: (404) 385-1746
Email: mooney@ece.gatech.edu
WWW: http://www.ece.gatech.edu/users/mooney/


RESEARCH INTERESTS

System-Level Design of Core-based Hardware-Software Systems; Synthesis and Specification of Embedded Systems; Specification and Computer-Aided Design of Digital Systems; Real Time Operating Systems; Probabilistic Computing; VLSI Systems; Logic Design; Computer Architecture and Distributed Computer Systems.

EDUCATION

9/92-9/98
Stanford University, Stanford, CA.
Ph.D. in Electrical Engineering, 6/98. Ph.D. Area: Hardware/Software Co-Design.
Master of Arts in Philosophy, Symbolic Systems Program, 6/97.
Master of Science in Electrical Engineering, 6/94.
10/91-6/92
University of Navarra, San Sebastian, Spain.
Certificate of Graduate Study. Research Assistant with the Electrical Engineering department, worked on the design & development of a real-time vision system.
9/87-5/91
Yale University, New Haven, Connecticut.
Bachelor of Science in Electrical Engineering and in Computer Science (2 majors), Cum Laude.

EXPERIENCE

5/04-present
Associate Professor, School of Electrical and Computer Engineering, College of Engineering, Adjunct Associate Professor, School of Computer Science, College of Computing, Georgia Institute of Technology.
Directs hardware/software co-design research group. Teaches classes in logic design, VLSI design, logic synthesis, high-level synthesis and core-based hardware/software co-design.
7/10-7/11
Visiting Associate Professor, School of Computer Engineering, College of Engineering, Nanyang Technological University.
7/08-7/11
Visiting Associate Professor, School of Electrical and Electronic Engineering, College of Engineering, Nanyang Technological University.
Deputy Director, Institute of Sustainable and Nanoelectronics. Taught classes in VLSI design, logic synthesis, high-level synthesis and core-based hardware/software co-design.
7/98-5/04
Assistant Professor, School of Electrical and Computer Engineering, College of Engineering, Adjunct Assistant Professor, College of Computing, Georgia Institute of Technology.
Directs hardware/software co-design research group. Teaches classes in logic design, VLSI design, logic synthesis, high-level synthesis and core-based hardware/software co-design.
7/95-6/98,
1/94-6/94
Research Assistant, Professor Giovanni De Micheli, Computer Systems Laboratory, Stanford University.
Research in Computer Aided Design for mixed hardware/software systems. Developed a Run-Time Scheduler for such systems, with an emphasis on predictably satisfying system level constraints, such as relative timing constraints and rate constraints. The Run-Time Scheduler is a mixed implementation partly in hardware and partly in software.
1/95-6/95
Research Assistant, Dr. Richard Reis, Executive Director, Center for Integrated Systems and Stanford Integrated Manufacturing Association research centers, Stanford University.
Interview professors and prepare materials for forthcoming book on preparing for an academic career in engineering or the sciences.
10/94-12/94, 10/93-12/93, 10/92-6/93
Teaching Assistant, Electrical Engineering Department and Computer Science Department, Stanford University, Stanford, CA.
Classes TAed: CS143, Introduction to Compilers; EE271, Introduction to VLSI Systems; EE284, Queueing Theory; EE218, Semi-Custom VLSI Systems; EE282, Computer Architecture.
Led discussion sections and provided help for classes of 30 to 150 students. Created exam questions and graded exams.
Summers 93-94
Applications Engineer Intern, Redwood Design Automation, San Jose, CA (now Alta Group of Cadence Design Systems, Foster City, CA).
Developed GNU debugger on top of a Verilog sparc model for hardware/software co-design using Race/Reveal product. Tested examples for Hardware Design System product (1994).
Developed automatic regression tests for system level simulator product. Evaluated product functionality from user perspective. Qualified customer problem reports and identified workarounds (1993).
Summer 92
Software Intern, Software Development Group, Hughes Network Systems, Germantown, MD.
Added features to a 10,000 line Operating System, written in C, that operated the handset of an air to ground telephone system.
Summer 91
Engineering Intern, VLSI Design Group, Allied Signal Aerospace Company, Columbia, MD.
Designed high fault coverage test vectors for cells of their VLSI standard cell library.
Summers 87-90
Summer Intern, AT&T Bell Laboratories, NJ, MA, PA and IL.
With Affirmative Action group, wrote programs to make availability calculations for the various Bell Labs job classifications. Attended and evaluated a racial sensitivity course required for all Bell Labs management. Learned about AA/EEO/Diversity issues (1990).
Performed Failure Mode Analysis on some of the HIC's being produced. Built an overload pulse test set to detect voids in thin film resistors (1989).
Designed and built a hardware bench test set for Failure Mode Analysis of an ASIC responsible for telephone line scanning (1988).
Implemented and tested the effects of modifying the line scan rate on dial tone delay and call capacity (1987).

Click to see my publications so far.

PROFESSIONAL CONTRIBUTIONS

Academic Publicity Chair, FPGAworld Conference, 2013
Academic Program Chair, FPGAworld Conference, 2005-2012
Program Chair, International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), October 2012
Program Co-Chair, International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), October 2011
Special Session Organizer & Chair, International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), October 2010
Special Session Organizer & Chair, Asian and South Pacific Design Automation Conference (ASP-DAC), January 2010
Special Session Organizer & Chair, International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), October 2009
Program Co-Chair, Workshop on Embedded Systems Security (WESS), October 2009
General Chair, IFIP International Conference on VLSI and System-on-a-Chip, October 2007
Keynote Speaker, FPGA World Conference, September 2007
Keynote Speaker, Global Open-Source Programmable Logic (GOSPL) Conference, October 2004
Keynote Speaker, FPGA World Conference, September 2004
Program Co-Chair, IFIP International Conference on VLSI and System-on-a-Chip, December 2003
Publicity Vice-Chair, International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), 2000
Publicity Co-Chair, 20th Anniversary Conference on Advanced Research in VLSI (ARVLSI), 1999

HONORS

ARCS 2012 Best Paper Award, 3/12.
U.S. Air Force Summer Faculty Fellowship, 5/07-8/07.
Senior Member, IEEE, 12/03
ASP-DAC 2003 Best Paper Award Candidate, 1/03.
National Science Foundation Career Award, 6/00.
Design Automation Conference (DAC) Graduate Scholarship, 6/00.
National Semiconductor Fellowship, 9/97 - 6/98.
Honorable Mention, National Defense Science & Engineering Graduate Fellowship Program, 4/93 & 4/94.
AT\&T Engineering Scholarship Program (1 of 15 awarded yearly in U.S.), 9/87 - 5/91.
NCAA Postgraduate Scholar (1 of 29 awarded yearly in U.S.), 5/91.
Jim Clarke Award for excellence in and enthusiasm for EE, 5/91.

EXTRACURRICULARS

Senior Member - Institute of Electrical and Electronics Engineers, 11/03-present.
Member - Association for Computing Machinery, 6/96-present.
Faculty Advisor - College Republicans at Georgia Tech, 8/2012-present.
Faculty Advisor - Georgia Tech Students for Life, 8/2001-2008.
Mentor - Valley Scholars Mentor Program (for high school), 9/97-6/98.
Founding member and Board - Link Institute (for education), 9/96-6/01.
Mentor - New Stanford EE Student Mentor Program, 10/93-6/97.
Founding member and Co-President - Stanford True Love Waits, 10/94-3/97.
Member - Institute of Electrical and Electronics Engineers, 6/94-11/03.
Liaison - Stanford Center for Teaching and Learning, 10/93-6/94.
Tutor - Terman Tutoring Program at Stanford, 10/92-12/92.
Member - Stanford Society of Chicano/Latino Engineers and Scientists, 10/92-6/98.
Member - Stanford Students for Life, 10/92-6/96.
Prop - Rugby team, Athletic Club of San Sebastian, Spain, 10/91-5/92.
Center and Guard - Yale Varsity Football team, 1/88-12/90.
Center - Yale Freshman Football team, 9/87-12/87.
Member - Yale Students of Mixed Racial and Ethnic Descent, 9/89-5/91.
President - Yale Students for Life, 5/89-12/90.
Staff - International Forum at Yale, 1/90-5/90.
Contributing Writer - Yale Political Magazine, 1/89-5/89.
Member - Yale Science and Engineering Association, 1988-2000.